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| TA1383AFG TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1383AFG NTSC Chroma Decoder, Multi-Point Scan Sync Processor, H/V Frequency Counter IC for Color TV TA1383AFG integrates an NTSC chroma decoder, multi-point scan sync processor (equivalent to pin D4), and H/V frequency counter in a 30-pin flat package. The IC is ideal for double scan TVs. The baseband signal processing block incorporates sub adjustment circuits and a RGB/Y color difference matrix. The sync processor block supports 525I/P, 750P, and 1125I. TA1383AFG incorporates the I2C bus. The device can control various functions via the bus line. Weight: 0.63 g (typ.) Features Luminance block * Chroma trap * Y delay line Chroma block * NTSC decoder * TOF Baseband block * Sub contrast * * * * * * * * Sub tint Sub color Y delay line Offset adjustment ADC pre-filter (LPF) +6dB amp (ON/OFF) YCbCr/YPbPr/RGB input supported YCbCr/YPbPr output switchable Sync block * High-performance sync separator (at NTSC (525I) ) * * * * * * * Horizontal sync (15.734 k, 31.5 k, 33.75 k, 45 kHz) Vertical sync playback function (525I/P, 750P, 1125I) 2- and 3-level sync separator circuit HD/VD input (positive and negative polarities) HD/VD output (positive and negative polarities switchable) Horizontal/vertical frequency counting function Copy guard 1 2005-09-05 TA1383AFG Block Diagram D-SYNC1/Y3/G IN DIGITAL GND APC FILTER Cb/Pb/B IN VCC2 (5 V) Cb/Pb OUT Cr/Pr/R IN Cr/Pr OUT 3.58 X'tal HD OUT fsc OUT GND2 Y OUT 30 29 28 27 26 25 24 23 22 21 20 19 C2 IN 18 17 16 CLAMP CLAMP CLAMP TEST fsc CW U 3.58 VCXO APC C SW HD OUT SW HD PHASE SW SUB-CONT /AMP Y Y-DL1 LPF YCbCr/ YPbPr MATRIX OFFSET OFFSET SUB-COLOR /AMP DEMO V TOF ACC TEST YUV MATRIX V LPF U SUB TINT INTEG SW H/V-FREQ COUNTER HD (RGB MODE) TEST Y-DL2 525p 750p 1125i SYNC SW H/ V-SEPA H SW V-C/D VD OUT SW 525i: 8fH OTHERS:2fH H-RAMP SYNC SEPA C TRAP 525i NTSC SYNC SEPA V SW Y SW NOISE DET PULSE REMAKE PULSE REMAKE SYNC TIP CLAMP MONITOR OUT 7 HD IN 8 MONITOR OUT H-AFC H-C/D I C BUS VCO 2 SYNC TIP CLAMP 1 VCC1 (9 V) 2 Y1/SYNC1 IN SYNC OUT 3 SYNC OUT SYNC TIP CLAMP 4 Y2/SYNC2 IN 5 VD IN 6 D-SYNC2 IN (for freq. det.) 9 AFC FILTER 10 HVCO 11 GND1 12 ADDRESS 13 SDA 14 SCL 15 VD OUT 2 C1 IN 2005-09-05 TA1383AFG Pins (unless otherwise specified, VCC1 = 9 V, VCC2 = 5 V, Ta = 25C) Pin No. 1 Symbol Function VCC for sync separation block, outputs, and interface. Connects 9 V (typ.). Interface I/O Signal 1 Vp-p (with Sync) Y signal input pin. Inputs NTSC (525I) signal via clamp capacitor. 2 4 Y1/SYNC1 IN Y2/SYNC2 IN Sync signal is separated from Y signal input to this pin. Can also be used for sync-only input pins. When not used, leave open. 2 4 1 k 30 k 1 Sync-Tip: 2.0 V 9 pF VCC1 (9 V) 1 k 1 k 1 k 1 k 2V 5 A 11 1 3 SYNC OUT Outputs sync-separated C-SYNC. Open collector output. 3 100 High/Low 11 1 25 A Th: 0.7 V Inputs vertical sync VD signal. 5 VD IN Inputs positive- and negative-polarity signals. When not used, leave open. 1 k 5 45 k 1.5 V or Th: 0.7 V 11 1 Vp-p (with Sync) Sync-Tip: 2.0 V 1 1 k Inputs Y signal for identifying frequency. 6 D-SYNC2 IN (for freq. det.) Inputs Y signals such as 525IP, 720P, and 1125I via clamp capacitor. When not used, leave open. 6 1 k or 1 k 11 1 Th: 0.7 V Inputs horizontal sync HD signal. 7 HD IN Inputs positive- and negative-polarity signals. When not used, leave open. 500 7 50 k or Th: 0.7 V 11 3 2005-09-05 TA1383AFG Pin No. Symbol Function Interface I/O Signal 1 500 Monitor output pin. 8 MONITOR OUT Emitter follower output. Selects output signal according to bus setting. 500 8 5 k 11 1 6.3 V 36 k 9 AFC FILTER Connects horizontal AFC filter. Voltage of this pin determines horizontal output frequency. 300 9 11 1 Use Murata CSBLA503KECZF30 or CSBFB503KJCZF60. 1 k 10 10 k 11 11 GND1 GND pin for 9-V block. 1 7.5 V 1 k 12 1.5 V 4.5 V 30 k 60 k 60 k 15 k Switches slave addresses. Slave addresses are set according to voltage of this pin. 12 ADDRESS VCC (9 V): DEH/DFH 6 V: DCH/DDH 3 V: DAH/DBH GND: D8H/D9H VCC (9 V) 7.5 V 4.5 V 1.5 V GND 1 k 10 HVCO 2 k Connects ceramic oscillator for horizontal oscillation. 4 k VCC: DEH/DFH 6 V: DCH/DDH 3 V: DAH/DBH GND: D8H/D9H 11 1 ACK 11 1 2.25 V 14 SCL I C bus SCL pin. 2 5 k 14 SCL 2.25 V 13 SDA I C bus SDA pin. 2 50 13 5 k SDA 11 4 2005-09-05 TA1383AFG Pin No. Symbol Function Interface I/O Signal 1 500 Vertical sync VD output pin. 50 k 50 k 15 VD OUT Emitter follower output. Sets polarity of output signal according to bus setting. 15 or 5 k 11 25 16 16 19 C1 IN C2 IN Inputs chroma signal via clamp capacitor. When not used, leave open. 1 k 19 18 k 18 k 1 k Burst: 300 mVp-p 27 1 500 Horizontal sync HD output pin. 50 k 50 k 17 HD OUT Emitter follower output. Sets polarity of output signal according to bus setting. 17 or 5 k 11 18 DIGITAL GND GND pin for digital block. 1.8 k 25 APC Del 1 k 20 APC FILTER 2.4 V 3 k Connects APC filter for chroma demodulation. 20 2 k 2.4 V 27 25 21 3.58 MHz X'tal Connects recommended 3.58-MHz oscillator for chroma demodulation. 2.5 k 21 500 27 5 2005-09-05 TA1383AFG Pin No. Symbol Function Interface I/O Signal 1 500 Cr/Pr 22 23 24 Cr/Pr OUT Cb/Pb OUT Y OUT Output Y, Cb, and Cr, or Y, Pb, and Pr signals. Emitter follower output. Set output format and amplitude according to bus setting. 22 23 24 2 mA Cb/Pb Y 11 25 VCC2 (5 V) VCC for Y, chroma, and baseband processing block. Connects 5 V (typ.). 25 200 AC: 600 mVp-p fsc carrier wave (CW) output pin. 26 CW OUT Emitter follower output. 26 200 Color: 3.0 V B/W: 1.3 V 1 mA 27 27 GND2 GND pin for 5-V block 1 Inputs 525I/P, 1125I, and 750P Cr/Pr/R and Cb/Pb/B signal via clamp capacitor. 28 29 Cr/Pr/R IN Cb/Pb/B IN Set input format according to bus setting. When not used, connect 0.1 F between this pin and GND. 28 29 700 mVp-p 1 k Cr/Pr 1 k 1 k 2.3 V Cb/Pb 11 1 Inputs 525I/P, 750P, and 1125I Y signal or G signal via clamp capacitor. D-SYNC1/Y3/G IN 1 k Sync signal is separated from Y (G) signal input to this pin. Set input format according to bus setting. When not used, connect 0.1 F between this pin and GND. 30 1 k 1 k 1 k 1 k 2V 1 k 1 Vp-p (with Sync) 30 Y 2.3 V 5 A 11 6 2005-09-05 TA1383AFG Bus Control Map Write Data SA 00 01 02 03 04 05 06 07 08 09 0A 525I-SEP GAIN SW D7 READ SW FREQ DET SW AFC-MODE MATRIX SW HD-POL VD-POL SUB-CONT SUB-COLOR SUB-TINT Y BLACK ADJ Cr BLACK ADJ Cb BLACK ADJ Y-DL1 Slave Address: D8/DA/DC/DEH D6 D5 INPUT SW H-SEP LVL NOISE LVL BANDWIDTH C-TRAP V-MODE HD POSI TOF f0 TOF Q Y-DL2 D4 D3 D2 H/V FREQ V-SEP LVL D1 D0 AFC-RAN D-SY2 SEP LVL MONITOR TEST Preset 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Note 1: SA: Sub-Address Read Data Slave Address: D9/DB/DD/DFH Read Mode 1 (read SW = 1) D7 0 1 POR SYNC-IN D6 COLOR Y1/2-IN D5 C-GUARD Y3-IN D4 N-DET D-SYNC2 D3 V-STD H-STAB D2 H-LOCK V-SYNC D1 HD-OUT ACC D0 VD-OUT V-SKEW Read Mode 2 (read SW = 0) D7 0 1 C-SYNC D6 D5 D4 D3 V FREQUENCY DET H FREQUENCY DET D2 D1 D0 7 2005-09-05 TA1383AFG Bus Control Functions Write Function Signal Switches Read Mode. Switches Read Mode. 0: READ MODE 2 (counts frequency) 1: READ MODE 1 (self diagnosis) Switches luminance, chroma, and sync signals. 000: SYNC1/Y1/C1 INPUT SW 010: SYNC2/Y2/C2 100: D-SYNC1/Y3/CbCr (PbPr) 110: HD/VD/Y3/CbCr (PbPr) 001: SYNC2/Y1/C1 011: SYNC2/Y3/CbCr (PbPr) 101: D-SYNC1/RGB 111: HD/VD/RGB SYNC1/Y1/C1 (000) Function Power-On Initial Value Self diagnosis (1) READ SW Switches horizontal oscillation frequency and vertical pull-in range. 000: Horizontal oscillation frequency 15.734 kHz, vertical pull-in range 224.5H to 297H (262.5H at quiescent) 001: Horizontal oscillation frequency 31.5 kHz, vertical pull-in range 48H to 612H (525H at quiescent) 010: Horizontal oscillation frequency 33.75 kHz, vertical pull-in range 48H to 636H (562.5H at quiescent) 011: Horizontal oscillation frequency 45 kHz, vertical pull-in range 48H to 848H (750H at quiescent) 100: Horizontal oscillation frequency 15.734 kHz, forced vertical pull-in range 262.5H 101: Horizontal oscillation frequency 15.734 kHz, vertical pull-in range 32.5H to 297H (at multi-windows) 110: D5 (1125P/60 Hz) input mode (H: 33.75 kHz Free-run, V: 48H to 636H) Internal clamping pulse, internal H-BLK and HD output are generated by inputted sync. When no-signal inputted, the clamp pulse, the H-BLK and VD output are switched to free-run signals of 33.75 kHz/562.5H. And then, HD output is gone. Set AFC-Mode = (111) and INPUT SW = (100), when this mode used. 111: RGB Input Mode (H frequency 33.75 kHz Free-run, V pull-in range 48H to 740H) Input HD signal is used as clamp pulse. HD/VD-OUT outputs are remade of input signals. (H-pull-in range: 5.7 kHz to 120 kHz, V-pull-in range: 47 Hz to 688 Hz, HD input width: 0.2 s to 10 s, VD input width: 3 s to 1.45 ms) When no-signal inputted, the clamp pulse, the H-BLK and VD output are switched to free-run signals of 33.75 kHz/562.5 H. And then, HD output is gone. Set AFC-Mode = (111) and INPUT SW = (111), when this mode used. In this mode, when TEST = 01, V-pull-in range becomes 0 to 688 Hz. Then, VD output is gone when no-input. Switches horizontal AFC pull-in range. Switches pull-in range of 525I/P, 750P, and 1125I horizontal frequencies. 0: NORMAL 1: Narrow NORMAL (0) H: 15.734 kHz V: 224.5H to 297H (000) H/V FREQ AFC-RAN Switches frequency counting input. Switches input pin for counting frequency. 00: 525I1 (rejects pulse of 1.75 s or less.) (pins 2, 4, and 30) 01: 525I2 (inputs H-sync for AFC. (and rejects pulse of 0.3 s or less.) ) (pins 2, 4, and 30) FREQ DET SW 10: D-SYNC2 (pin 6) 11: HD/VD (pins 5 and 7) Note: To count frequency, use Bus Mode (10/11). However, note that in Bus Mode (00/01), frequencies such as 525P, 750P, and 1125I cannot be counted. In this mode (00/01), frequencies may not be counted accurately due to weak electric fields or ghosts. D-SYNC2 (10) 8 2005-09-05 TA1383AFG Signal Function Switches sync separation level of horizontal sync signal. Switches sync separation level of horizontal sync signal input to sync input pins. H-SEP LVL At 525I At 525P 00: 20% 01: 27% 10: 34% 11: 40% 00: 20% 01: 30% 10: 40% 11: 50% 20% (00) Power-On Initial Value Three-level sync 00: 25% 01: 35% 10: 45% 11: 55% Switches sync separation level of vertical sync signal. Switches sync separation level of vertical sync signal input to sync input pins. 40% V-SEP LVL At 525I At 525P Three-level sync 00: 40% 01: 50% 00: 20% 01: 30% 00: 25% 01: 35% 10: 60% 11: 70% 10: 40% 11: 50% 10: 45% 11: 55% 20% (00) (00) Switches sync separation level of D-SYNC2 IN (pin 6). D-SY2 SEP LVL Switches sync separation level of sync signal input to pin 6. 00: 20% 01: 30% 10: 40% Switches AFC gain. Switches AFC gain setting mode. 000: AUTO1 (normal: 0dB, at skew: +6dB, at noise: -12dB) 001: AUTO2 (AUTO1 + prevention against AFC disoperation at noise + stabilization of AFC in weak electric field + ghost prevention) 010: AUTO3 (Video input mode: AUTO2 + 0dB at V-SKEW detected) AFC-MODE 011: AUTO4 (RF input mode: AUTO2 + 0dB at V-SKEW detected, however, -12dB at normal. Also, AFC gain is not controlled by noise detection result) 100: Forced +6dB 101: Forced 0dB 110: Forced -12dB 111: Forced Off (horizontal free running) Note: Set AUTO1 to 4 according to input signal status. Switches noise detection level. NOISE LVL Switches noise detection level. Noise is detected only in NTSC signals (525I). Noise detection result is reflected in BUS READ and AFC-GAIN operation (as in AUTO1 to 3 modes). 00: max 11: min 11: 50% Forced +6dB (100) max (00) Switches MONITOR output. Switches signal output from MONITOR OUT (pin 8). Field identification output is valid for 525I and 1125I standard signal. 000: 1-bit DAC output (high) 001: 1-bit DAC output (low) MONITOR 010: Field identification output (ODD: low, EVEN: high) (000) 011: Noise detection output 100: V sync separation output at 525I 101: Skew detection output 110: Clamp pulse output 111: H/V-SYNC at D-SYNC2 input DAC HIGH 9 2005-09-05 TA1383AFG Signal Switches 525I SEP Mode Switches H-SEP Mode. (Countermeasure ghost signal) 525I-SEP 0: ON Automatically controls that H-SEP level does not go higher than V-SEP level, the initial value is 40%. 1: OFF Switches matrix. Sets I/O signal format for input pins (28, 29, and 30) and output pins (22, 23, and 24). 00: MODE-1 (YC1/YC2 YCbCr, Y3/CbCr YCbCr, RGB YCbCr) MATRIX SW 01: MODE-2 (YC1/YC2 YCbCr, Y3/PbPr YCbCr, RGB YCbCr) 10: MODE-3 (YC1/YC2 YPbPr, Y3/CbCr YPbPr, RGB YPbPr) 11: MODE-4 (YC1/YC2 YPbPr, Y3/PbPr YPbPr, RGB YPbPr) Note: Set this function together with INPUT SW, H/V FREQUENCY for each input signal. Switches bandwidth limiting filter (ADC pre-filter). Sets bandwidth of bandwidth limiting filter and image mute. BANDWIDTH 00: OFF (through) 01: Filter 1 (Y: 10.3 MHz/-3dB, Cb/Cr: 4.2 MHz/-3dB) 10: Filter 2 (Y: 14.6 MHz/-3dB, Cb/Cr: 6.5 MHz/-3dB) 11: Image mute (Y: -20IRE, CbCr: 0IRE) Switches vertical sync playback mode. Switches VD OUT (pin 15) sync playback mode. 0: PLL Mode for standard signals V-MODE 1: Direct Sync Mode PLL for standard signals (0) OFF (00) (00) (1) OFF Function Power-On Initial Value Note 1: Setting 0 is valid only for standard signals. For other signals, set to Direct Sync Mode. In PLL Mode for standard signals, VD output starts with 4-s delay in relation to V-SYNC. For other signals, 0.25-H delay. Note 2: Set this register to (1) except inputting the NTSC and 525I composite sync format. TEST Shipment Test Mode. When TEST = 01 and H/V FREQ = 111, V-pull-in range is expanded (Refer to H/V FREQ function explanation). In other case, set to 00. Switches output gain. (00) 0dB GAIN SW Sets output amp gain for pins 22, 23, and 24. 0: +6dB 1: 0dB Positive polarity (0) (1) Switches HD output polarity. HD-POL Sets HD OUT (pin 17) polarity. 0: Positive polarity 1: Negative polarity Switches VD output polarity. VD-POL Sets VD OUT (pin 15) polarity. 0: Positive polarity Switches chroma trap. C-TRAP Switches chroma trap for image signals input to pins 2 and 4. 1: Negative polarity Positive polarity (0) OFF (0) 0: OFF 1: ON Adjusts HD output phase. Sets output phase of HD OUT (pin 17). HD POSI 0000: 800 ns (2.7% of H cycle) ahead of sync center 1111: Sync center Note: Sync center is based on 33.75 kHz/3-level sync. (0000) 10 2005-09-05 TA1383AFG Signal Adjusts subcontrast. SUB-CONT Adjusts amplitude of output Y signal (pin 24). 00000: min (-3dB) 11111: max (+3dB) Function Power-On Initial Value CENTER (10000) Switches TOF center frequency. TOF f0 Controls center frequency of chroma filter for chroma signals input to pins 16 and 19. 000: OFF Adjusts sub color. SUB-COLOR Adjusts amplitude of output Cb/Cr (Pb/Pr) signals (pins 22 and 23). 00000: min (-3dB) 11111: max (+3dB) 001: min (0.56 fsc) 111: max (1.05 fsc) CENTER (10000) OFF (000) Switches TOF Q characteristic. TOF Q Controls center frequency of chroma filter for chroma signals input to pins 16 and 19. 000: min (0.6) Adjusts sub tint. CENTER SUB-TINT Adjusts tint for output Cb/Cr (Pb/Pr) signals (pins 22 and 23). 0000: min (-7 deg) 1111: max (+7 deg) (1000) 111: max (1.2) min (000) Adjusts Y delay time 1 (baseband block). Y-DL1 Switches delay amount of Y signal in baseband block. 00: -10 ns 01: 0 ns 10: +10 ns 11: +10 ns -10 ns (00) Note: Sets delay amount according to settings such as BANDWIDTH. Adjusts Y delay time 2 (NTSC Y processing block). Y-DL2 Switches delay amount of Y signal in NTSC Y processing block. 00: OFF 01: +40 ns 10: +80 ns 11: +120 ns OFF (00) Note: Sets delay amount according to settings such as TOF f0/Q. Adjusts Y black level. Y BLACK ADJ Adjusts black level offset of Y OUT (pin 24). 00000000: OFF 00000001: min (-140 mV) Adjusts Cb (Pb) black level. Cb BLACK ADJ Adjusts black level offset of Cb (Pb) OUT (pin 23). 00000000: OFF 00000001: min (-140 mV) Adjusts Cr (Pr) black level. Adjusts black level offset of Cr (Pr) OUT (pin 22). Cr BLACK ADJ 00000000: OFF 00000001: min (-140 mV) 11111111: max (+140 mV) (10000000) CENTER 11111111: max (+140 mV) CENTER (10000000) 11111111: max (+140 mV) CENTER (10000000) Read Function Signal Power-on reset POR 0: RESISTER PRESET 1: NORMAL Function After power on, 0 is returned at first read; 1, at second and subsequent reads. Detects NTSC color or BW (Black and White). COLOR 0: BW 1: NTSC color 11 2005-09-05 TA1383AFG Signal Detects copy guard (pseudo SYNC). C-GUARD 0: No copy guard detected 1: Copy guard detected Function Detects whether input signal has copy-guard signal in the systems of 60-Hz 525 I/P, 60-Hz 1125 I, and 60-Hz 750 P, but does not detect copy-guard of HD/VD input signal. Detects noise. N-DET 0: Small amount detected 1: Large amount detected Set noise detection level in NOISE LEVEL. N-DET is detected only when 525I Y or CVBS signal is input. Detects NTSC standard/non-standard. V-STD 0: Standard detected 1: Non-standard detected Detects vertical-sync-signal input in standard cycle. V-STD is detected only when 525I Y or CVBS signal is input. Detects H-LOCK. 0: Unlock detected H-LOCK 1: Lock detected Detects lock/unlock of input signal and H-AFC. H-LOCK is detected in the systems of 60-Hz 525 I/P, 60-Hz 1125 I, and 60-Hz 750 P. Note: This register may show UN-LOCK, when H-SYNC width of 525I Y or CVBS input is narrow. HD-OUT Detects HD-OUT (pin 17) self-diagnosis. 0: NG (no signal) 1: OK (signal detected) Detects VD-OUT (pin 15) self-diagnosis. VD-OUT 0: NG (no signal) 1: OK (signal detected) Detects SYNC IN (pins 2 and 4 or 30) self-diagnosis. SYNC-IN 0: NG (no signal) At small signal, NG. Detects Y1/2 IN (pin 2 or 4) self-diagnosis. Y1/2-IN 0: NG (no signal) At small signal, NG. Detects Y3 IN (pin 30) self-diagnosis. Y3-IN 0: NG (no signal) At small signal, NG. Detects D-SYNC2 IN (pin 6) self-diagnosis. D-SYNC2 0: NG (no signal) At small signal, NG. Detects stability of horizontal signal. H-STAB 0: Stable 1: Not stable 1: OK (signal detected) 1: OK (signal detected) 1: OK (signal detected) 1: OK (signal detected) Determines not stable when fluctuation of horizontal signal is detected within one field. H-STAB is detected only when 525I Y or CVBS signal is input. Detects vertical sync of input signal. V-SYNC 0: No vertical sync detected 1: Vertical sync detected Detects whether input signal has vertical sync. V-SYNC is detected in the systems of 60-Hz 525 I/P, 60-Hz 1125 I, and 60-Hz 750 P. Detects status of automatic color control (ACC) circuit. ACC 0: Maximum 1: Other ACC is detected only when NTSC signal is input. 12 2005-09-05 TA1383AFG Signal Detects vertical skew of VCR. V-SKEW 0: no skew 1: skew Function V-SKEW is detected only when NTSC signal is input. Detects 2-/3-level sync of D-SYNC2 IN (pin 6). C-SYNC 0: 2-level sync 1: 3-level sync Detects sync width per 1H. Note: If 525I/P 60-Hz signal has half SYNC width or less, 3-level sync may be determined. Counts vertical frequency of signal selected by FREQ DET SW. 0000000 to 0011100: No VD 0011101: Vicinity of 195 Hz 1111111: Vicinity of 44.6 Hz How to calculate vertical frequency (X); V FREQUENCY DET Converts data read from V-FREQ DET into decimal value and calls value Y. Z = 176.54 s. Vertical frequency (X) = 1 / (Y x Z) [Hz] Vertical frequency error is Y = -1 to +1. When vertical frequency is 195 Hz or more, frequency cannot be counted accurately. Note that time constant used to integrate C.SYNC then separate V-SYNC is 9 s (error 1 s). Data read first time after power on are undefined. Counts horizontal frequency of signal selected by FREQ DET SW. 00000000: Quiescent 11111111: 120 kHz or more How to calculate horizontal frequency (X); X, Y, and Z are defined the same as those for vertical frequency. H FREQUENCY DET Horizontal frequency (X) = Y / (12 x Z) [kHz] Horizontal frequency error is Y = -1 to +2. When horizontal frequency is 120 kHz or more, frequency cannot be counted accurately. When horizontal frequency is approx. 142 kHz to approx. 200 kHz, data are read as 00000000 by the timing of counting. When V-SYNC or VD is not input, horizontal frequency cannot be counted. Data are read as 00000000. Data read first time after power on are undefined. Note 1: To count horizontal or vertical frequency, data are read between the first V-SYNC/VD and the second V-SYNC/VD following the reset pulse generated at the second byte as the start trigger. To stabilize data, set the bus read interval to 3 V or longer. Discard the data read the first time because they are undefined. However the frequency is counted when BUS is read at Read Mode 1. Therefore the data that is BUS read at Read Mode 2 is valid. Note 2: Even when Read Mode 1 is switched to Read Mode 2, set the BUS read interval to 3 V or longer. Figures of BUS read interval at Read Mode 2 Start trigger 1 Read Timing More than 3 V V-SYNC or VD Data 1 and Start trigger 2 Data 2 and Start trigger 3 Counting period 1 (to data 1) Counting period 2 (to data 2) Figures of BUS read interval at Read Mode 2 Note 3: Though there is no restriction for setting BUS read interval at Read Mode 1, set the interval to 1 V per one period at shortest to read the data accurately. Decision algorithm (detection range, detection times and so on) for H/V frequency detection should be determined under consideration of forward Notes and the other factors such as signal strength, existence of ghost signal, APC stability, I2C BUS data transmission and so on via prototype TV set evaluation. 13 2005-09-05 TA1383AFG How To Start I C Bus After power on, TA1383FG pins 28 and 29 (Cr/Pr/R IN, Cb/Pb/B IN) are in Full-Field Clamp Mode. Full-Field Clamp Mode is released by writing or reading. And then, clamp is performed only during the clamp pulse period. Described below is how to send bus data after power on. Use software to handle the procedure. 1. Turn power on. 2. Transmit all write data. 2 How To Transmit/Receive Via I C Bus Slave Address: Can Be Changed Using Pin 12. (VCC1 = 9 V, VCC2 = 5 V) Pin 12-GND (GND to 1.2 V): D8H/D9H A6 1 A5 1 A4 0 A3 1 A2 1 A1 0 A0 0 W/R 0/1 2 Pin 12-3 V (1.8 to 4.2 V): DAH/DBH A6 1 A5 1 A4 0 A3 1 A2 1 A1 0 A0 1 W/R 0/1 Pin 12-6 V (4.8 to 7.2 V): DCH/DDH A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W/R 0/1 Pin 12-VCC1 (7.8 to VCC1) DEH/DFH A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 1 W/R 0/1 Start and Stop Conditions SDA SCL S Start condition P Stop condition Bit Transmission SDA SCL SDA must not be changed SDA may be changed Acknowledgement SDA from transmitter SDA from receiver Low impedance at bit 9 only SCL from master S Clock pulse for acknowledgement 1 8 9 High impedance at bit 9 14 2005-09-05 TA1383AFG Data Transmit Format 1 S Slave address 7-bit MSB S: Start condition 0A Sub address 8-bit MSB A: Acknowledgement A Transmit data 8-bit MSB P: End condition AP Data Transmit Format 2 S Slave address 0A Sub address A Transmit data 1 A A AP Sub address Transmit data n Data Receive Format S Slave address 7-bit MSB 1A Receive data 1 8-bit MSB A Receive data 2 AP MSB To receive data, the master transmitter changes to the receiver immediately after the first acknowledgement. The slave receiver changes to the transmitter. The end condition is always created by the master. Optional Data Transmit Format Auto Increment Mode 1 S Slave address 7- bit MSB 0A1 Sub address 7-bit A Transmit data 8-bit MSB MSB Auto Increment Mode 2 S Slave address 7-bit MSB 0A1 Sub address 7-bit A Transmit data 1 8-bit MSB Transmit data n 8-bit MSB AP MSB In this way, sub addresses are automatically incremented from the specified sub address and data are set. 15 2005-09-05 TA1383AFG I2C BUS Conditions Characteristics Low level input voltage High level input voltage Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min 0 1.8 0 Typ. Max 1.0 Vcc 0.4 10 10 100 Unit V V V -10 0 4.0 4.7 4.0 4.7 350 250 4.0 4.7 A pF kHz s s s s ns ns s s 16 2005-09-05 TA1383AFG Maximum Ratings (Ta = 25C) Characteristics Supply voltage Input pin voltage Power dissipation Power dissipation reduction rate depending on temperature Operating temperature Storage temperature Symbol VCCmax Vin PD (Note 4) 1/ja Topr Tstg Rating 12 GND - 0.3 to VCC + 0.3 1471 11.8 Unit V V mW mW/C -20~65 -55~150 C C Note 4: See the figure below. (the figure is based on when the IC is mounted on a board of 50 x 50 x 1.6 mm and 30% Cu area. this is the minimum board size.) Note 5: Misoperation may be caused in the IC due to leakage from high electric fields generated by the CRT. Install the IC at least 20 cm from the CRT. If not possible, use a shield to shield electric fields. 1471 (mW) Power dissipation PD 1000 0 0 25 65 150 Ambient temperature Ta (C) Figure Power dissipation reduction curve 17 2005-09-05 TA1383AFG Operating Conditions Characteristic Supply voltage (VCC) Y signal input amplitude Chroma signal input amplitude Cb, Cr (Pb, Pr) signal input amplitude R, G, B signal input amplitude HD, VD signal amplitude Syncronization HD input width RGB mode Frequency detection Syncronization VD input width RGB mode Frequency detection HD input frequency VD input frequency SYNC OUT input current pin 1 pin 25 pins 2, 4, 6, 30 including sync pins 16, 19 burst signal amplitude pins 28, 29 100% color bar signal pins 28, 29, 30 100% white signal pins 5, 7 Pin 7, H/V FREQ = 000 to 101 Pin 7, H/V FREQ = 111 Pin 7 Pin 5, H/V FREQ = 000 to 101 Pin 5, H/V FREQ = 111 Pin 5 Pin 7, H/V FREQ = 111 Pin 5, H/V FREQ = 111 Pin 3 DE/DFH Address switching voltage Pin 12 DC/DDH DA/DBH D8/D9H SCL/SDA pull-up voltage SDA input current Pin 13,14 Pin 13 Description Min 8.5 4.7 Typ. 9.0 5.0 1.0 300 700 700 5 Max 9.5 5.3 Unit V Vp-p mVp-p mVp-p mVp-p Vp-p 1.2 0.5 s 0.2 0.2 s 3 s 3 s 3 5.7 47 6 0.2 H 10 0.2 H (Note 6) 31 H 1.45 ms 400 120 688 1.6 9 6.75 9 6 3 0 5 s s kHz Hz mA 8.25 5.25 2.25 0 2.5 V 3.75 0.75 7.5 2 V mA Note 6: The ratio of H-cycle for HD input for frequency detection. Electrical Characteristics values) (unless otherwise specified, VCC1 = 9 V, VCC2 = 5 V, Ta = 25C 3C, bus data: preset Current Dissipation Pin Name VCC1 (9 V) VCC2 (5 V) Symbol ICC1 ICC2 Test Circuit Min 29.3 52.9 Typ. 36.5 66.0 Max 44.4 80.2 Unit mA mA Pin Voltage Pin No. 2 4 22 23 24 28 29 30 Y1/SYNC1 IN Y2/SYNC2 IN Cr/Pr OUT Cb/Pb OUT Y OUT Cr/Pr/R IN Cb/Pb/B IN YD-SYNC1/Y3/G IN Pin Name Symbol V2 V4 V22 V23 V24 V28 V29 V30 Test Circuit Min 1.7 1.7 3.15 3.15 2.85 2.0 2.0 1.7 Typ. 2.0 2.0 3.50 3.50 3.20 2.3 2.3 2.0 Max 2.3 2.3 3.85 3.85 3.55 2.6 2.6 2.3 Unit V V V V V V V V 18 2005-09-05 TA1383AFG Y/Cb/Cr Block Characteristics Y input dynamic range Symbol VDY VDY30 Color difference input dynamic range Chroma trap characteristic (00) Y delay time switching 1 (pre-filter block) (01) (10) (11) (01) Y delay time switching 2 (TOF block) (10) (11) Y I/O gain 1 (YCbCr YCbCr) Cb Cr Y BY BB I/O gain 2 (YPbPr YCbCr) BR RY RB RR Y BY BB I/O gain 3 (YCbCr YPbPr) BR RY RB RR Y I/O gain 4 (YPbPr YPbPr) Pb Pr GY GB GR BY I/O gain 5 (RGB YCbCr) BB BR RY RB RR VDCb VDCr GCT YDY100 YDY101 YDY110 YDY111 YDL2A YDL2B YDL2C GMYC GMBC GMRC GMYC1 GMBC1 GMBC2 GMBC3 GMRC1 GMRC2 GMRC3 GMYP1 GMBP1 GMBP2 GMBP3 GMRP1 GMRP2 GMRP3 GMYP GMBP GMRP GMGA1 GMGA2 GMGA3 GMBA1 GMBA2 GMBA3 GMRA1 GMRA2 GMRA3 Test Circuit Test Condition Pins 2, and 4 Pins 30 Pin 28 Pin 29 fsc attenuation SA07H: 80H SA07H: 84H SA07H: 88H SA07H: 8CH SA07H: 81H SA07H: 82H SA07H: 83H SA03H: 80H, Between pins 30 and 24 SA03H: 80H, Between pins 29 and 23 SA03H: 80H, Between pins 28 and 22 Min 1.35 1.26 1.0 1.0 Typ. 1.50 1.40 Max 1.65 1.54 Unit Vp-p -10 0 10 10 40 80 120 0.00 0.00 0.00 0.00 -20 -5 5 13 13 55 110 160 1.00 1.00 1.00 1.00 Vp-p dB -17 -5 7 7 30 70 100 ns ns -1.00 -1.00 -1.00 -1.00 -21.4 -1.1 -25.5 -14.1 -21.1 -1.2 -1.00 -20.0 -0.8 -24.5 -14.4 -20.8 -0.8 dB -19.9 -0.1 -24.0 -13.1 -19.1 -0.2 0.00 -18.4 0.9 (Note Y1) -22.5 -12.1 -17.6 0.9 1.00 dB -18.5 0.2 -17.0 1.2 (Note Y2) -22.5 -13.4 -18.8 0.22 0.00 0.00 0.00 -20.5 -12.4 -17.3 1.2 1.00 1.00 1.00 dB SA03H: E0H, Between pins 30 and 24 SA03H: E0H, Between pins 29 and 23 SA03H: E0H, Between pins 28 and 22 -1.00 -1.00 -1.00 -5.0 -10.6 -8.6 -20.4 -7.0 -25.0 -10.5 -16.5 -7.0 dB -4.0 -9.6 -7.6 -18.9 -6.0 -23.0 -9.5 -15.5 -6.0 -3.0 -8.6 -6.6 -17.4 -5.0 -21.0 -8.5 -14.5 -5.0 dB (Note Y3) 19 2005-09-05 TA1383AFG Characteristics GY GB GR BY I/O gain 6 (RGB YPbPr) BB BR RY RB RR Filter 1 Pre-filter 1 (Y axis) Filter 2 GFY4 GFBR1 Filter 1 Pre-filter 2 (B-Y, R-Y axes) Filter 2 GFBR4 Positive Y black-level range Negative R-Y, B-Y black-level range Output gain switching Y I/O gain (Y1/Y2 IN) Sub contrast characteristic Sub color characteristic Input crosstalk max Tint characteristic min Y1/Y2 Frequency characteristic Y3 Cb/Cr TNTMIN GY1IN GY3IN GBRIN max min max min Positive Negative YBMIN RBBMAX RBBMIN GGSW GY GSCMAX GSCMIN GCLMAX GCLMIN GCLT TNTMAX YBMAX GFBR2 GFBR3 GFY2 GFY3 Symbol GMGB1 GMGB2 GMGB3 GMBB1 GMBB2 GMBB3 GMRB1 GMRB2 GMRB3 GFY1 Test Circuit Test Condition Min Typ. Max Unit SA03H: 88H, at 11.3 MHz SA03H: 88H, at 16 MHz SA03H: 90H, at 16 MHz SA03H: 80H, at 27 MHz SA03H: 88H, at 5.65 MHz SA03H: 88H, at 16 MHz SA03H: 90H, at 8 MHz SA03H: 90H, at 27 MHz SA08H: FFH, pin 24 SA08H: 01H, pin 24 SA09H/10H: FFH, pin 23/22 SA09H/10H: 01H, pin 23/22 SA04H: 00H/80H Between pins 2/4 and 24 SA05H: F8H/80H SA05H: 80H/00H SA06H: F8H/80H SA06H: 80H/00H (Note Y4) -3.1 -9.3 -7.9 -22.8 -7.0 -29.0 -13.5 -21.0 -7.0 -8 -30 -11 -34 -8 -42 -8 -48 126 -2.1 -8.3 -6.9 -21.8 -6.0 -27.0 -12.5 -19.0 -6.0 -4 -18 -4 -26 -5 -35 -5 -35 140 -1.1 -7.3 -5.9 -20.8 -5.0 -25.0 -11.5 -17.0 -5.0 -1 -9 -1 -18 -2 -28 -2 -26 154 mV dB dB dB -154 126 -140 140 -126 154 -154 5 -140 6 0 3.0 -126 7 1.0 4.0 mV dB dB dB -1.0 2.0 -4.0 2.0 -3.0 3.0 -2.0 4.0 -4.0 -35 6.0 -3.0 -50 7.0 -2.0 8.0 dB dB SA07H: F0H/80H SA70H: 80H/00H at 13 MHz, Input; pins 2 and 4 at 40 MHz, Input; pin 30 at 40 MHz, Input; pins 28 and 29 -8.0 -2 -2 -2 -7.0 0 0 0 -6.0 2 2 2 dB 20 2005-09-05 TA1383AFG Chroma Block Characteristics Symbol F601 F301 ACC characteristic F31 F11 A1 Color difference output level B R VBO VRO RRB Test Circuit Test Condition Min 280 280 (Note CH1) 270 115 0.85 600 100% color bar 600 100% color bar, Cb/Cr 0.93 705 1 0 90 90 5.4 4.6 840 1.15 3 93 93 10.0 mV 3.5 Pins 16 and 19: AC GND (Note C3H) Upper hold range Upper pull-in range Lower hold range Lower pull-in range Pin 26 Pin 26 at NTSC input Pin 26 at quiescent Pins 22 and 23, fsc leakage level, when rainbow signal (B = C = 300 mVp-p) input Pins 22 and 23, 2 x fsc leakage level when rainbow signal (B = C = 300 mVp-p) input 6.0 MHz Hz/mV 3.579345 3.579545 3.579745 Typ. 330 330 320 130 1.00 720 Max 380 380 370 145 1.15 840 Unit mVp-p mVp-p Color difference output relative amplitude B Demodulation angle R Color difference output relative phase Identification sensitivity Free-running frequency APC frequency control sensitivity Hold + APC pull-in and hold ranges Pull-in + Hold - Pull-in - CW output amplitude High CW output DC level Low Killer OFF Killer ON B R BR VCI VBI f03 (Note CH2) -3 87 86 4.0 f f3HH f3PH f3HL f3PL Vfsc V26H V26L 0.5 250 250 1.0 500 500 1.5 2000 2000 -2000 -2000 400 2.7 1.0 -500 -500 600 3.0 1.3 -250 -250 720 3.3 Hz mVp-p V 1.6 Residual carrier wave level VNE 4.0 mVp-p Residual harmonic level VHNE 4.0 mVp-p 0 kHz TOF characteristic GFH GFC GFL GF+ GF- 19 (Note CH4) 17 14 14 (Note CH5) 22.5 21 19 16 16 24.5 23 21 18 18 dB 26.5 dB +500 kHz -500 kHz TOF (f0Q) control characteristic f0+ f0- 21 2005-09-05 TA1383AFG Sync Block Characteristics SYNC IN sync phase SYNC1/2 D-SYNC1 HD IN horizontal sync phase 15.73 kHz Delayed HD pulse width 31.5 kHz 33.75 kHz 45 kHz 00 NTSC horizontal sync separation level 01 10 11 00 NTSC vertical sync separation level 01 10 11 00 1125I/60-Hz horizontal sync separation level 01 10 11 00 1125I/60-Hz vertical sync separation level 01 10 11 00 D-SYNC2 sync separation level 01 10 11 HD input threshold 15.73 kHz-1 31.5 kHz 33.75 kHz-1 45 kHz Horizontal free-running frequency 15.73 kHz-2 15.73 kHz-3 33.75 kHz-2 33.75 kHz-3 15.73 kHz-4 15.73 kHz-1 Symbol SPH DS1PH HDPH Wd-HD0 Wd-HD1 Wd-HD2 Wd-HD3 VthH10 VthH11 VthH12 VthH13 VthV10 VthV11 VthV12 VthV13 VthH20 VthH21 VthH22 VthH23 VthV20 VthV21 VthV22 VthV23 VthD20 VthD21 VthD22 VthD23 VthHD FA000 FA001 FA010 FA011 FA100 FA101 FA110 FA111 FF000 F15MIN F15MAX F31MIN F31MAX F33MIN F33MAX F45MIN F45MAX 15.73 kHz-2 F15nMIN F15nMAX Test Circuit Test Condition (Note SY01) (Note SY02) Min 2.8 0.75 0.8 3.9 (Note SY03) 1.4 1.3 1.5 0.219 (Note SY04) 0.199 0.179 0.162 0.157 (Note SY05) 0.129 0.1 0.072 0.059 (Note SY06) 0.080 0.109 0.135 0.059 (Note SY07) 0.080 0.109 0.135 0.056 (Note SY08) 0.086 0.111 0.134 Pin 7 0.6 15.59 31.19 33.41 44.55 (Note SY09) 15.59 15.59 33.41 33.41 15.59 14.37 16.61 28.97 33.23 (Note SY10) 30.91 35.44 41.81 48.27 14.80 16.06 Typ. 3.0 0.85 0.9 4.2 1.6 1.5 1.7 0.229 0.209 0.189 0.169 0.172 0.143 0.114 0.086 0.070 0.091 0.120 0.146 0.070 0.091 0.120 0.146 0.067 0.097 0.122 0.145 0.7 15.73 31.5 33.75 45 15.73 15.73 33.75 33.75 15.73 14.67 16.94 29.56 33.90 31.54 36.15 42.62 49.24 15.10 16.36 Max 3.2 0.95 1.0 4.6 1.8 1.7 1.9 0.239 0.219 0.199 0.179 0.186 0.157 0.129 0.1 0.081 0.102 0.131 0.157 0.081 0.102 0.131 0.157 0.078 0.108 0.133 0.156 0.8 15.91 31.82 34.09 45.45 15.91 15.91 34.09 34.09 15.91 14.97 17.27 30.15 34.57 32.17 36.86 43.48 50.21 15.40 16.66 kHz kHz V Vp-p Vp-p Vp-p Vp-p Vp-p Unit s s s 31.5 kHz Horizontal frequency range 33.75 kHz 45 kHz 22 2005-09-05 TA1383AFG Characteristics 15.73 kHz Horizontal oscillation control sensitivity 31.5 kHz 33.75 kHz 45 kHz 0dB ID1- AFC phase detection current ID2+ ID2- Symbol BH1573 BH315 BH3375 BH45 ID1+ Test Circuit Test Condition Min 2.7 Pin 9 voltage vs horizontal oscillation frequency 5.4 5.6 7.9 256 256 56 (Note SY11) 56 536 536 Pin 1 (VCC1) NTSC signal, MONITOR OUT (pin 9) 4.0 70 670 670 4.6 1 10 87.5 838 838 4.9 V H Typ. 3.4 6.7 7.0 9.7 320 320 70 Max 4.1 8.0 8.4 11.5 400 400 87.5 kHz/V Unit pin 7: HD input pin 17: Monitor (Note SY13) Pin 17: High voltage Pin 17: Low voltage (Note SY12) -6dB A -12dB VCO oscillation start voltage AFC phase detection stop period Start Stop 15.73 kHz Ph 15.73 kHz W 31.5 kHz Ph 31.5 kHz W 33.75 kHz Ph HD output phase and width 33.75 kHz W 45 kHz Ph 45 kHz W D5 mode Ph D5 mode W RGB mode Ph RGB mode W High HD output level Low 15.73 kHz ID3+ ID3- VVCO TVMASK1 TVMASK2 HDS0 HDW0 HDS1 HDW1 HDS2 HDW2 HDS3 HDW3 HDS4 HDW4 HDS5 HDW5 HDVH HDVL -1.0 4.3 -0.6 4.7 0.14 2.45 0.08 2.3 0.13 1.8 0.33 2.3 0.2 2.47 5.3 0.3 1.6 1.43 0.81 0.72 0.78 0.66 0.56 0.50 50 -0.8 4.5 0.04 2.25 -0.06 2.05 -0.12 1.9 -0.02 2.1 0.03 1.6 0.23 2.1 0.1 2.35 5.1 0.1 1.45 1.30 0.74 0.65 0.71 0.60 0.51 0.45 45 50 -0.07 1.4 0.13 1.9 0 2.23 4.9 0 1.31 1.17 0.67 0.59 0.64 0.54 0.46 0.41 40 45 s V V HP0- HP0+ HP1- HP1+ HP2- HP2+ HP3- HP3+ HD-DUTY1 HD-DUTY2 31.5 kHz HD output phase adjustment range 33.75 kHz s 45 kHz HD input polarity detection range (-) (+) (+) (-) % 55 23 2005-09-05 TA1383AFG Characteristics 15.73 kHz Symbol CPS0 CPW0 31.5 kHz CPS1 CPW1 33.75 kHz Clamp pulse phase and width 45 kHz CPS2 CPW2 CPS3 CPW3 D5 mode CPS4 CPW4 RGB mode Clamp pulse output level High Low 00; 1 0 01; 1 0 10; 1 0 Noise detection 11; 1 0 00; 0 1 01; 0 1 10; 0 1 11; 0 1 High DAC output voltage Low VD input threshold 525I-1 525P 1125I VD output width 750P 525I-2 525I-3 1125P 525I-1 525P VD output phase 1125I 750P 525I-1b High VD output level Low VDVL VDACL0 VthVD VDW000 VDW001 VDW010 VDW011 VDW100 VDW101 VDW110 VDPh000 VDPh001 VDPh010 VDPh011 VDPh000b VDVH CPS5 CPW5 CPVH CPVL NHi00 NHi01 NHi10 NHi11 NLow00 NLow01 NLow10 NLow11 VDACH1 Test Circuit Test Condition Min 6.15 1.8 2.85 0.9 1.85 (Note SY14) 0.9 1.95 0.9 0.75 0.4 0.05 2.23 4.7 pin 8, SA 02H: 86H 0 37 26 20 (Note SY15) 17 17 13 9 8 Pin 8, SA02H: 80H Pin 8, SA02H: 81H Pin 5 4.8 0 0.6 451 237 222 451 455 (Note SY16) 222 222 14.4 6.65 6.15 4.85 12 Pin 15: High voltage Pin 15: Low voltage 4.7 0 0.1 50 35 27 23 23 18 14 12 5 0.1 0.75 513 270 252 513 517 252 252 17.5 7.85 7.25 5.72 14 5.0 0.1 0.3 63 44 34 29 29 23 19 16 5.2 V 0.3 0.9 575 302 282 575 579 282 282 20.1 9.05 8.35 6.6 16 5.3 V 0.3 V mVp-p Typ. 6.35 2 2.95 1 1.95 1.0 2.05 1.0 0.85 0.5 0.15 2.35 5.0 Max 6.55 2.2 3.05 1.1 2.05 1.1 2.15 1.1 0.95 0.6 0.25 2.47 5.3 V Unit s s s 24 2005-09-05 TA1383AFG Characteristics 525I-1 525P 1125I 750P 525I-2 525I-3 1125P RGB 525I-1 525P 1125I 750P Vertical pull-in range 525I-2 525I-3 1125P RGB FVP100 FVP101 FVP110 FVP111 Symbol FVF000 FVF001 FVF010 FVF011 FVF100 FVF101 FVF110 FVF111 FVP000 FVP001 FVP010 FVP011 Test Circuit Test Condition Pin 15: Quiescent, SA00H: E0H Pin 15: Quiescent, SA00H: E2H Pin 15: Quiescent, SA00H: E4H Pin 15: Quiescent, SA00H: E6H Pin 15: Quiescent, SA00H: E8H Pin 15: Quiescent, SA00H: EAH Pin 15: Quiescent, SA00H: ECH Pin 15: Quiescent, SA00H: EEH Pin 15, SA00H: 80H Pin 15, SA00H: 82H Pin 15, SA00H: 84H Pin 15, SA00H: 86H Pin 15, SA00H: 88H Pin 15, SA00H: 8AH Pin 15, SA00H: 8CH Pin 15, SA00H: EEH Min Typ. 262.5 525 562.5 750 262.5 296.5 562.5 562.5 Max Unit 224 48.5 48.5 48.5 H Vertical free-running frequency 296.5 612 636 848 H 262.5 32 48.5 48.5 296.5 636 740 25 2005-09-05 TA1383AFG Test Method (unless otherwise specified, VCC1 = 9 V, VCC2 = 5 V, Ta = 25C 3C, bus data: preset values) Note No. Y/back end block Characteristic SW28 SW Mode SW29 SW30 Y/back end block common test conditions (1) (2) (3) Y1 I/O gain 2 (YPbPr YCbCr) C A C A C (5) (6) (7) A (1) (2) (3) (4) Write data: Transmit PREST DATA. Read data: Read DATA. Set SA 08H/09H/10H to 00H/00H/00H. Set SW2 to A, SW4 to A, SW6 to B, SW9 to On, SW12 to A, SW16 to A, SW19 to A, SW22 to B, SW23 to B, and SW24 to B. Set INPUT SW (SA 00H) to D-SYNC1/Y3/CbCr (PbPr) (C0H). Set MATRIX SW (SA 03H) to MODE-2 (A0H). Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p. Measure #24 amplitude VMYC [V] and determine GMYC using the following equation. GMYC = 20 x log (VMYC/0.2) [dB] Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p. Input sync signal to IN30. Measure #24, #23, #22 amplitudes VMBC1, VMBC2, and VMBC3 [V], and determine GMBC1, GMBC2, and GMBC3 using the following equation. GMBC* = 20 x log (VMBC*/0.2) [dB] (8) (9) Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz), and set #28 amplitude to 0.2 Vp-p. Input sync signal to IN30. Test Method (10) Measure #24, #23, #22 amplitudes VMRC1, VMRC2, and VMRC3 [V], and determine GMRC1, GMRC2, and GMRC3 using the following equation. GMRC* = 20 x log (VMRC*/0.2) [dB] 26 2005-09-05 TA1383AFG Note No. Y2 I/O gain 3 (YCbCr YPbPr) Characteristic SW28 C A SW Mode SW29 C A C (5) (6) (7) SW30 A (1) (2) (3) (4) Set INPUT SW (SA 00H) to D-SYNC1/Y3/CbCr (PbPr) (C0H). Set MATRIX SW (SA 03H) to MODE-3 (C0H). Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p. Measure #24 amplitude VMYP [V] and determine GMYP using the following equation. GMYP = 20 x log (VMYP/0.2) [dB] Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p. Input sync signal to IN30. Measure #24, #23, #22 amplitudes VMBP1, VMBP2, and VMBP3 [V], and determine GMBP1, GMBP2, and GMBP3 using the following equation. GMBP* = 20 x log (VMBP*/0.2) [dB] (8) (9) Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz) to IN28, and set #28 amplitude to 0.2 Vp-p. Input sync signal to IN30. Test Method (10) Measure #24, #23, #22 amplitudes VMRP1, VMRP2, and VMRP3 [V], and determine GMRP1, GMRP2, and GMRP3 using the following equation. GMRP* = 20 x log (VMRP*/0.2) [dB] Y3 I/O gain 5 (RGB YCbCr) C A C A C (5) (6) (7) A (1) (2) (3) (4) Set INPUT SW (SA 00H) to DSYNC1/RGB (D0H). Set MATRIX SW (SA 03H) to MODE-1 (80H). Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p. Measure #24, #23, #22 amplitudes VMGA1, VMGA2, and VMGA3 [V], and determine GMGA1, GMGA2, and GMGA3 using the following equation. GMGA* = 20 x log (VMGA*/0.2) [dB] Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p. Input sync signal to IN30. Measure #24, #23, #22 amplitudes VMBA1, VMBA2, and VMBA3 [V], and determine GMBA1, GMBA2, and GMBA3 using the following equation. GMBA* = 20 x log (VMBA*/0.2) [dB] (8) (9) Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz) to IN28, and set #28 amplitude to 0.2 Vp-p. Input sync signal to IN30. (10) Measure #24, #23, #22 amplitudes VMRA1, VMRA2, and VMRA3 [V], and determine GMRA1, GMRA2, and GMRA3 using the following equation. GMRA* = 20 x log (VMRA*/0.2) [dB] 27 2005-09-05 TA1383AFG Note No. Y4 I/O gain 6 (RGB YPbPr) Characteristic SW28 C A SW Mode SW29 C A C (5) (6) (7) SW30 A (1) (2) (3) (4) Set INPUT SW (SA 00H) to DSYNC1/RGB (D0H). Set MATRIX SW (SA 03H) to MODE-4 (E0H). Input sine wave A (f = 100 kHz) to IN30 and set #30 amplitude to 0.2 Vp-p. Measure #24, #23, #22 amplitudes VMGB1, VMGB2, and VMGB3 [V], and determine GMGB1, GMGB2, and GMGB3 using the following equation. GMGB* = 20 x log (VMGB*/0.2) [dB] Set SW29 to A, input sine wave B (f = 100 kHz) to IN29, and set #29 amplitude to 0.2 Vp-p. Input sync signal to IN30. Measure #24, #23, #22 amplitudes VMBB1, VMBB2, and VMBB3 [V], and determine GMBB1, GMBB2, and GMBB3 using the following equation. GMBB* = 20 x log (VMBB*/0.2) [dB] (8) (9) Set SW28 to A and SW29 to C, input sine wave B (f = 100 kHz), and set #28 amplitude to 0.2 Vp-p. Input sync signal to IN30. Test Method (10) Measure #24, #23, #22 amplitudes VMRB1, VMRB2, and VMRB3 [V], and determine GMRB1, GMRB2, and GMRB3 using the following equation. GMRB* = 20 x log (VMRB*/0.2) [dB] 28 2005-09-05 TA1383AFG Note No. Chroma block Characteristic SW Mode SW2 SW30 Chroma block common test conditions (1) (2) CH1 ACC characteristic B C (1) (2) (3) (4) Write data: Transmit PREST DATA. Read data: Read DATA. Set SW2 to B, SW4 to C, SW6 to B, SW9 to On, SW12 to A, SW16 to A, SW19 to A, SW22 to B, SW23 to B, and SW24 to B, SW28 to C, SW29 to C, and SW30 to C. Input sync signal (15.734 kHz) to TP2. Input rainbow signal to the C1 IN pin (burst: chroma = 1:1). Adjust burst phase so that the lower extremity of the TP23A (Cb/Pb OUT) output waveform is at the second bar; the upper extremity, at the 7th bar. Change the chroma input signal amplitudes to 10, 30, 300, and 600 mVp-p and measure the TP23A (Cb/Pb OUT) output amplitudes F11, F31, F301, and F601. Determine A2 = F31/F601 according to the measurement result in (3) above. Test Method TA23A output signal waveform F30, F300, 6 1 2 3 45 7 8 9 10 F600 F10 10 30 300 600 TA23A (Cb/Pb OUT) output signal waveform Input rainbow signal to the C1 IN pin (burst: chroma = 1:1). Monitor TP26 (CW OUT) DC voltage. C1 IN signal amplitude [mVp-p] CH2 Identification sensitivity B C (1) (2) (3) (4) Increase input signal amplitude from 0. When TP26 (CW OUT) DC voltage reaches High (3.2 V), measure input signal amplitude VCI. Decrease input signal amplitude from 100 mVp-p. When TP26 (CW OUT) DC voltage drops Low (1.4 V), measure input signal amplitude VBI. Connect #20 (APC FILTER) to external power supply (V20). Change external power supply (V20) voltage. When #26 (CW OUT) output frequency matches 3.579545 MHz, voltage is referred to as Vf. Measure #26 (CW OUT) output frequency Xf (+100) and Xf (-100) in relation to Vf Vf (100 mVp-p). Determine free-running sensitivity f using the following equation. f = (Xf (+100) - Xf (-100))/200 [Hz/mV] CH3 APC frequency control sensitivity C C (1) (2) (3) 29 2005-09-05 TA1383AFG Note No. CH4 Characteristic TOF characteristic SW Mode SW2 B SW30 C (1) (2) (3) (4) (5) (6) Input sine wave C (10 mVp-p) to C1 IN pin. Set TEST (SA 03H) to 82H and TINT (SA 07H) to 30H. Set TOF f0 (SA 05H) to 87H (f0 max) and TOF Q (SA 06H) to 87H (Q max). Set sine wave C frequency to 3.58 MHz, measure TP26 (CW OUT) signal amplitude, and determine input gain GFC. Set sine wave C frequency to 3.58 MHz + 500 kHz, measure TP26 (CW OUT) signal amplitude, and determine input gain GFH. Set sine wave C frequency to 3.58 MHz - 500 kHz, measure TP26 (CW OUT) signal amplitude, and determine input gain GFL. Test Method TP output signal waveform GFH GFC GFL f0 - 500 kHz f0 f0 + 500 kHz C IN input frequency Input sine wave C (f0 = 3.579545 MHz, amplitude = 10 mVp-p) to C1 IN pin. Set TEST (SA 03H) to 82H and TINT (SA 07H) to 30H. Set TOF f0 (SA 05H) to 87H (f0 = max) and TOF Q (SA 06H) to 80H (Q min), measure CW OUT (TP26) signal amplitude, and determine input gain GFF. Set TOF f0 (SA 05H) to 81H (f0 = min) and TOF Q (SA 06H) to 87H (max). Measure CW OUT (TP26) signal amplitude, and determine input gain GFQ. CH5 TOF (f0q) control characteristic B C (1) (2) (3) (4) (5) 30 2005-09-05 TA1383AFG Note No. Sync block Characteristic SW2 SW Mode SW4 SW9 SW30 Sync block common test conditions (1) (2) SY01 SYNC IN sync phase A or C A or C ON A or C (1) (2) (3) (4) (5) (6) (7) (8) Write data: Transmit PREST DATA. Read data: Read DATA. Set SW6 to B, SW12 to A, SW16 to B, SW19 to B, SW22 to B, SW23 to B, and SW24 to B, SW28 to B, and SW29 to B. Set SA 00H data to 80H (or 90H). Set SW2 to A (or C), SW4 to C (or A), and SW30 to C. Input composite video signal of 15.734-kHz horizontal frequency to Y1/SYNC1 IN (or Y2/SYNC2 IN). Monitor #2 (or #4) pin waveform and #9 (AFC FILTER) pin waveform. Measure phase difference SPH. Set SW2 to C, SW4 to C, and SW30 to A. Input signal a to D-SYNC1/Y3 IN. Set SA 00H data to C4H. Monitor #30 pin waveform and #9 (AFC FILTER) pin waveform. Measure phase difference DS1PH. 29.63 s 2 s Signal a 0.286 V SPH, DS1PH #9 Pin Waveform Test Method 31 2005-09-05 TA1383AFG Note No. SY02 Characteristic SW2 HD IN horizontal sync phase C SW Mode SW4 C SW9 ON SW30 A (1) (2) (3) (4) Set SA 00H data to E2H. Input signal b (horizontal frequency 31.5 kHz) to #7 (HD IN). Set SA 02H data to 02H. Monitor #7 and #9 (AFC FILTER) pin waveforms. Measure phase difference HDPH. 31.75 s 2.35 s Signal b 1.5 V HDPH #9 Pin Waveform Test Method 32 2005-09-05 TA1383AFG Note No. SY03 Characteristic SW2 Delayed HD pulse width C SW Mode SW4 C SW9 ON SW30 A (1) (2) (3) (4) (5) (6) (7) (8) Set SA 00H data to C0H and input 15.734-kHz composite video signal to D-SYNC1/Y3 IN. Determine pulse width Wd-HD0 of delayed HD from #9 (AFC FILTER) pin waveform. Set SA 00H data to C2H and input signal c (T = 31.75 s, t = 2.35 s) to D-SYNC1/Y3 IN. Determine pulse width Wd-HD1 of delay HD from #9 (AFC FILTER) pin waveform. Set SA 00H data to C4H and input signal c (T = 29.63 s, t = 2 s) to D-SYNC1/Y3 IN. Determine pulse width Wd-HD2 of delay HD from #9 (AFC FILTER) pin waveform. Set SA 00H data to C6H and input signal c (T = 22.22 s, t = 1.65 s) to D-SYNC1/Y3 IN. Determine pulse width Wd-HD3 of delay HD from #9 (AFC FILTER) pin waveform. T t Signal c 0.286 V Wd-HD* #9 Pin Waveform Test Method 33 2005-09-05 TA1383AFG Note No. SY04 NTSC horizontal sync separation level Characteristic SW2 A SW Mode SW4 C SW9 ON SW30 C (1) (2) (3) (4) (5) (6) (7) (8) (9) Set SA 00H data to 80H. Input 15.734-kHz composite video signal to Y1/SYNC1 IN. Set sync signal amplitude to 0.286 Vp-p. Decrease horizontal sync signal amplitude of line 21 of field 1 in pedestal direction. Monitor #3 (SYNC OUT). When no sync signal on line 21 of field 1 is detected, measure input signal sync amplitude of line 21, and determine sync separation level VthH10. Set SA 01H data to 90H. Repeat steps (3) and (4) above and determine sync separation level VthH11. Set SA 01H data to A0H. Repeat steps (3) and (4) above and determine sync separation level VthH12. Set SA 01H data to B0H. Test Method (10) Repeat steps (3) and (4) above and determine sync separation level VthH13. SY05 NTSC vertical sync separation level A C ON C (1) (2) (3) (4) (5) (6) (7) (8) (9) Set SA 00H data to 80H. Input 15.734-kHz composite video signal to Y1/SYNC1 IN. Set sync signal amplitude to 0.286 Vp-p. Decrease vertical sync signal amplitude of first half of line 4 of field 1 in pedestal direction. Monitor #15 (VD OUT). When VD pulse start phase shifts to line 5, measure input signal sync amplitude of line 4, and determine sync separation level VthV10. Set SA 01H data to 84H. Repeat steps (3) and (4) above and determine sync separation level VthV11. Set SA 01H data to 88H. Repeat steps (3) and (4) above and determine sync separation level VthV12. Set SA 01H data to 8CH. (10) Repeat steps (3) and (4) above and determine sync separation level VthV13. 34 2005-09-05 TA1383AFG Note No. SY06 1125I/60-Hz horizontal sync separation level Characteristic SW2 C SW Mode SW4 C SW9 ON SW30 A (1) (2) (3) (4) (5) (6) (7) (8) (9) Set SA 00H data to C4H. Input 33.75-kHz (1125I/60-Hz) video signal to D-SYNC1/Y3 IN. Monitor #30 (D-SYNC1/Y3 IN) and measure sync tip DC voltage Vsync30. Apply external voltage to #30 via 100 k. Increase voltage from Vsync30. Monitor #17 (HD OUT). When phase is unlocked from input sync signal, measure #30 sync tip voltage. Determine difference from Vsync30, VthH20. Set SA 01H data to 90H. Repeat steps (3) and (4) above and determine sync separation level VthH21. Set SA 01H data to A0H. Repeat steps (3) and (4) above and determine sync separation level VthH22. Set SA 01H data to B0H. Test Method (10) Repeat steps (3) and (4) above and determine sync separation level VthH23. SY07 1125I/60-Hz vertical sync separation level C C ON A (1) (2) (3) (4) (5) (6) (7) (8) (9) SA 00H data to C4H. Input 33.75-kHz (1125I/60-Hz) video signal to D-SYNC1/Y3 IN. Monitor #30 (D-SYNC1/Y3 IN) and measure sync tip DC voltage Vsync30. Apply external voltage to #30 via 100 k. Increase voltage from Vsync30. Monitor #17 (HD OUT). When phase is unlocked from input sync signal, measure #30 sync tip voltage. Determine difference from Vsync30, VthV20. Set SA 01H data to 84H. Repeat steps (3) and (4) above and determine sync separation level VthV21. Set SA 01H data to 88H. Repeat steps (3) and (4) above and determine sync separation level VthV22. Set SA 01H data to 8CH. (10) Repeat steps (3) and (4) above and determine sync separation level VthV23. 35 2005-09-05 TA1383AFG Note No. SY08 Characteristic SW2 DSYNC2 sync separation level C SW Mode SW4 C SW9 ON SW30 C (1) (2) (3) (4) (5) (6) (7) (8) (9) Set SW6 to A and set SA 00H data to 00H. Input 33.75-kHz (1125I/60) video signal to TP6 (D-SYNC2 IN). Monitor #6 (D-SYNC2 IN) and measure sync tip DC voltage Vsync6. Apply external voltage to #30 via 100 k. Increase voltage from Vsyn6. Monitor READ BUS DATA. When H/V FREQ data deviate from approx. 33.75 kHz/60 Hz, measure #6 sync tip voltage. Determine difference from Vsync6, VthD20. Set SA 01H data to 81H. Repeat steps (3) and (4) above and determine sync separation level VthD21. Set SA 01H data to 82H. Repeat steps (3) and (4) above and determine sync separation level VthD22. Test Method (10) Set SA 01H data to 83H. (11) Repeat steps (3) and (4) above and determine sync separation level VthD23. SY09 Horizontal free-running frequency C C OPEN C (1) (2) (3) (4) (5) (6) (7) (8) SY10 Horizontal frequency range C C OPEN C (1) (2) (3) (4) (5) Set SW9 to open and SA 00H data to 80H. Monitor #17 (HD OUT) pin waveform and measure oscillation frequency FA000. As in steps (1) and (2) above, set SA00H data to 82H, 84H, 86H, 88H, and 8AH. Measure respective oscillation frequencies FA001, FA010, FA011, FA100, and FA101. Set SA 00H data to 8CH, SA 02H to 83H, and SA 03H to 82H. Monitor #17 (HD OUT) pin waveform and measure oscillation frequency FA110. Set SA 00H data to 8EH, monitor #17 (HD OUT) pin waveform, and count oscillation frequency FA111. Set SA 00H data to 80H, SA 02H to E0H, and SA 03H to 80H. Monitor #17 (HD OUT) pin waveform and count oscillation frequency FF000. Set SW9 to open and SA 00H data to 80H. Apply 9 V to #9 via 10 k. Monitor #17 (HD OUT) pin waveform and count oscillation frequency F1573MIN. Apply 0 V to #9 via 10 k. Monitor #17 (HD OUT) pin waveform and count oscillation frequency F1573MAX. Set SA 00H data to 82H. As in steps (2) and (3) above, count oscillation frequencies F315MIN and F315MAX. Set SA 00H data to 81H. As in steps (2) and (3) above, count oscillation frequencies 1573nMIN and F1573nMAX. 36 2005-09-05 TA1383AFG Note No. SY11 Characteristic SW2 AFC phase detection current C SW Mode SW4 C SW9 OPEN SW30 C (1) (2) (3) (4) (5) (6) (7) (8) Set SA 00H to C0H and SA 02H to A0H. Set SW9 to open and measure #9 voltage V9 (6.3 to 6.4 V) (measure #9 voltage at no load). Connect external power supply (PS) to TP9 and apply V9. Set SW30 to A. Input 15.734-kHz sync signal d to D-SYNC1/Y3 IN. Monitor #9. Measure voltages V1 and V2. Set SA 02H data to C0H. Repeat steps (2) to (4) above. Measure voltages V3 and V4. Set SA 02H data to 80H. Connect external power supply (PS) to TP9 and apply V9 - 0.1 V and measure voltage V5. Connect external power supply (PS) to TP9 and apply V9 + 0.1 V and measure voltage V6. Determine ID1 to ID6 using following equations. ID1+ = (V1 [V] / 1 [k]) x 1000 [A] ID1- = (V2 [V] / 1 [k]) x 1000 [A] ID2+ = (V3 [V] / 1 [k]) x 1000 [A] ID2- = (V4 [V] / 1 [k]) x 1000 [A] ID3+ = (V5 [V] / 1 [k]) x 1000 [A] ID3- = (V6 [V] / 1 [k]) x 1000 [A] 63.5 s 4.7 s Signal d 0.286 V Test Method V1, V3, V5 #9 Pin Waveform V2, V4, V6 37 2005-09-05 TA1383AFG Note No. SY12 Characteristic SW2 HD output phase and width C SW Mode SW4 C SW9 ON SW30 A (1) (2) (3) (4) (5) (6) (7) (8) Set SA 00H data to C0H. Input 15.734-kHz composite video signal to D-SYNC1/Y3 IN. Measure #17 (HD OUT) and #30. Measure phase difference HDS0 and pulse width HDW0. Set SA 00H data to C2H. Input signal c (T = 31.75 s, t = 2.35 s) and measure phase difference HDS1 and pulse width HDW1. Set SA 00H data to C4H. Input signal c (T = 29.63 s, t = 2 s) to D-SYNC1/Y3 IN and measure phase difference HDS2 and pulse width HDW2. Set SA 00H data to C6H. Input signal c (T = 24.1 s, t = 1.65 s) to D-SYNC1/Y3 IN and measure phase difference HDS3 and pulse width HDW3. Set SA 00H data to CCH. Input signal c (T = 14.815 s, t = 1 s) to D-SYNC1/Y3 IN and measure phase difference HDS4 and pulse width HDW4. Set SA 00H data to FEH. Input signal c (T = 31.75 s, t = 2.35 s, amplitude = 1.5 V) to D-SYNC1/Y3 IN and measure phase difference HDS5 and pulse width HDW5. Test Method T t Signal c 0.286 V HDS* #17 Pin Waveform HDW* 38 2005-09-05 TA1383AFG Note No. SY13 Characteristic SW2 HD output phase adjustment range C SW Mode SW4 C SW9 ON SW30 C (1) (2) (3) (4) (5) (6) (7) (8) While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and measure #17 pin waveform phase amount HP0-. While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform phase amount HP0+. Set SA 00H data to 82H. While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and measure #17 pin waveform phase amount HP1-. While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform phase amount HP1+. Set SA 00H data to 84H. While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and measure #17 pin waveform phase amount HP2-. While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform phase amount HP2+. Set SA 00H data to 86H. While monitoring #17 (HD OUT), change SA 04H data from 80H to 88H, and measure #17 pin waveform phase amount HP3-. While monitoring #17 (HD OUT), change SA 04H data from 88H to 8FH, and measure #17 pin waveform phase amount HP3+. Test Method 39 2005-09-05 TA1383AFG Note No. SY14 Characteristic SW2 Clamp pulse phase and width C SW Mode SW4 C SW9 ON SW30 A (1) (2) (3) (4) (5) (6) (7) (8) (9) Set SA 00H data to C0H. Input 15.734-kHz composite video signal to D-SYNC1/Y3 IN. Set SA 02H data to 86H. Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS0 and width CPW0. Set SA 00H data to C2H. Input signal c (T = 31.75 s, t = 2.35 s) to D-SYNC1/Y3 IN. Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS1 and width CPW1. Set SA 00H data to C4H. Input signal c (T = 29.63 s, t = 2 s) to D-SYNC1/Y3 IN. Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS2 and width CPW2. Set SA 00H data to C6H. Input signal c (T = 22.22 s, t = 1.65 s) to D-SYNC1/Y3 IN. Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS3 and width CPW3. Test Method (10) Set SA 00H data to CCH. Input signal c (T = 14.815 s, t = 1.15 s) to D-SYNC1/Y3 IN. (11) Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS4 and width CPW4. (12) Set SA 00H data to FEH. Input signal c (T = 31.75 s, t = 2.35 s, amplitude = 1.5 V) to D-SYNC1/Y3 IN. (13) Monitor TP8 (MONITOR OUT) and #30 pin waveforms. Measure clamp pulse phase CPS5 and width CPW5. T t Signal c 0.286 V CPS* TP8 Pin Waveform CPW* SY15 Noise detection A C ON C (1) (2) (3) (4) Set SA 00H data to 80H. Input 500-kHz sine wave to Y1/SYNC2 IN. Increase sine wave amplitude from 0 Vp-p. When READ MODE 1 N-DET changes from 0 to 1, measure amplitude NHi00. Input 500-kHz sine wave to Y1/SYNC2 IN. Decrease sine wave amplitude from 1.0 Vp-p. When READ MODE 1 N-DET changes from 1 to 0, measure amplitude NLow00. As in steps (1) and (2) above, set SA 02H (NOISE LVL) data to 88H, 90H, and 98H, and measure respective amplitudes NHi01, NLow01, NHi0, NLow10, NHi11, and Nlow11. 40 2005-09-05 TA1383AFG Note No. SY16 Characteristic SW2 VD output width VD output phase C SW Mode SW4 C SW9 ON SW30 A (1) (2) (3) (4) (5) (6) (7) (8) (9) Set SA 00H data to C0H. Input 15.734-kHz composite video signal (525I/60-Hz) to D-SYNC1/Y3 IN. Monitor #30 and TP15 (VP OUT). Measure VD output width VDW000 and phase difference VDPh000. Set SA 00H data to C8H. Monitor #30 and TP15 (VP OUT). Measure VD output width VDW100. Set SA 00H data to CAH. Monitor #30 and TP15 (VP OUT). Measure VD output width VDW101. Set SA 00H data to C0H and SA 03H data to 84H. Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh000b. Set SA 00H data to C2H. Input 525P/60-Hz composite video signal to D-SYNC1/Y3 IN. Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh001 and width VDW001. Set SA 00H data to C4H. Input 1125I/60-Hz composite video signal to D-SYNC1/Y3 IN. Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh010 and width VDW010. Test Method (10) Set SA 00H data to C6H. Input 750P/60-Hz composite video signal to D-SYNC1/Y3 IN. (11) Monitor #30 and TP15 (VP OUT). Measure VD output phase difference VDPh110 and width VDW110. (12) Set SA 00H data to CCH. Input 1125P/60-Hz composite video signal to D-SYNC1/Y3 IN. (13) Monitor #30 and TP15 (VP OUT). Measure VD output width VDW110. Video Signal 525I-60 Hz or 525P-60 Hz TP15 Pin Waveform Video Signal 1125I-60 Hz VDPh000, VDPh000b, VDPh001 VDW000, VDPh001, VDW100, VDW101 VDPh010 TP15 Pin Waveform Video Signal 750P-60 Hz or 1125P-60 Hz TP15 Pin Waveform VDW010 VPPh011 VDW011, VDW110 41 2005-09-05 TA1383AFG Signals Used for Testing * Sine wave A * Sine wave B * Sync signal * Rainbow signal 180150120 90 60 30 0 -30-60-90 * Sine wave C * Composite video signal 15.743 kHz 42 2005-09-05 100 F 0.01 F Test Circuit Diagram VCC 9 V IN29 Cb IN IN28 Cr IN D-Sync1/Y3 IN 10 F IN30 Y1/Sync2 IN 10 F IN4 75 10 F 75 75 5.1 k 3.9 k 1.6 k 1.6 k 3.9 k 1.6 k 5.1 k 5.1 k 3.9 k 3.9 k 100 F 0.01 F 30 1 VCC1 (9 V) D-SYNC1/Y3/G IN B AC TP30 0.1 F #29 29 Cb/Pb/B IN #30 #2 0.1 F 2 Y1/SYNC1 IN Sync OUT #3 AC B B AC TP29 TP2 0.1 F #28 28 Cr/Pr/R IN 10 K 3 SYNC OUT #4 B AC TP28 0.1 F 27 GND2 0.1 F 4 AC B TP4 Y2/SYNC2 IN #26 26 CW TP26 OUT 5 TP26B #5 DV IN VD IN fsc OUT 0.1 F 100 0.01 F 100 F #6 6 D-SYNC2 IN (for freq. det.) VCC2 (5 V) Y1/Sync1 IN 10 F IN2 75 75 10 F 5.1 k 1.6 k 5.1 k 1.6 k 3.9 k 3.9 k TP26C TA1383AFG #24 #23 #22 Cr Cb Y OUT 25 24 OUT 23 OUT 22 #7 TP8 TP9 HD IN MONITOR 0.01 F TP24A TP23A TP22A 1 F 6.2 k TP6 D-SYNC2 IN 43 SW9 470 AB 1 k 100 B A D 15 k 15 k 15 k ADD C 470 SDA SCL VD OUT TP15 470 100 1.6 k TP24B AB 7 HD IN #8 8 MONITOR OUT #9 9 AFC FILTER #10 10 21 HVCO 3.58 X'tal Y OUT 100 Cb/Pb OUT 1.6 k TP23B AB 100 Cr/Pr OUT AB 100 #21 12 pF CSB503F30 #20 11 #12 12 #13 13 #14 14 #15 15 16 VD OUT C1 IN 17 SCL HD OUT SDA DIGITAL GND 19 ADDRESS C2 IN 18 20 GND1 APC FILTER 0.0022 F 30 k 0.22 F #19 #17 #16 BC A 0.1 F (Note 7) or 100 pF 100 0.1 F (Note 7) or 100 pF BC A TP19 75 2.2 k 1.6 k TP16 HD OUT TP17 1.6 k TP22B C2 IN IN19 75 3.58 MHz X'tal 2.2 k 1.6 k C1 IN IN16 0.01 F 100 F 10 F 2.7 k VCC 5 V 10 F 2.7 k Note 7: If there is a possibility of inputting CVBS signals, connect a 100-pF capacitor. TA1383AFG 2005-09-05 100 F 0.01 F 9V Cr IN Cb IN Y2/Sync2 IN Y1/Sync1 IN D-Sync2 IN 75 10 F 5.1 k 3.9 k 1.6 k Y2/Sync2 Y1/Sync1 1.6 k 1.6 k 1.6 k 3.9 k 3.9 k 3.9 k 1.6 k 5.1 k 5.1 k 5.1 k 10 F 10 F 10 F 75 75 75 75 0.01 F 5.1 k 3.9 k Cb Application Circuit 1 (Typical values) D-Sync1/Y3 IN 10 F 1.6 k 75 10 F 5.1 k 3.9 k Cr D-Sync2 100 F 0.01 F 1 0.1 F 2 Sync OUT Y1/SYNC1 IN Cb/Pb/B IN VCC1 (9 V) D-SYNC1/Y3/G IN 10 K 3 4 5 VD IN Y2/SYNC2 IN SYNC OUT Cr/Pr/R IN 0.1 F GND2 DV IN 0.1 F 6 fsc OUT D-Sync1/Y3 30 29 28 27 26 0.1 F 0.01 F 0.1 F #28 0.1 F 5V 0.01 F 100 F CW OUT 0.01 F 100 F 25 5V 9V Reg. 44 1 F HD IN MONITOR 0.01 F 6.2 k 470 HVCO B A D 15 k 15 k 15 k ADD C 470 SDA SCL VD OUT 470 D-SYNC2 IN (for freq. det.) VCC2 (5 V) Y OUT 24 7 8 9 10 11 12 13 14 15 HD IN Y OUT 100 23 MONITOR OUT Cb/Pb OUT Cb OUT 100 22 AFC FILTER Cr/Pr OUT TA1383AFG Cr OUT C2 IN 100 12 pF 21 HVCO 3.58 X'tal X'tal 75 2200 pF 20 GND1 APC FILTER 2.2 k 30 k 0.22 F 19 C2 IN ADDRESS 0.1 F (Note 8) or 100 pF 18 SDA DIGITAL GND 17 1.6 k C1 IN 75 10 F 2.2 k SCL HD OUT 1.6 k 16 VD OUT C1 IN 2.7 k HD OUT 0.1 F (Note 8) or 100 pF C2 IN C1 IN 0.01 F 10 F 2.7 k Note 8: If there is a possibility of inputting CVBS signals, connect a 100-pF capacitor. TA1383AFG 2005-09-05 TA1383AFG Application Circuit 2 (How to measure H/V frequency) 16 C1-IN 19 C2-IN Internal pulse (A) APC 6 D-SYNC2-IN (for H/V freq. counter) TA1383 FREQ COUNTER BUS READ This IC's H/V frequency counting is done by internal pulse (A) which is made in APC circuit. So, if APC circuit doesn't lock in the regular frequency, the frequency of pulse (A) will not be correct and the H/V frequency data will not be showed correct data. Decision algorithm of H/V frequency detection (detection range, detection times and so on) should be determined under consideration the factors such as signal strength, existence of ghost signal, APC stability, I2C BUS data transmission and so on via prototype TV set evaluation. 45 2005-09-05 TA1383AFG Package Dimensions Weight: 0.63 g (typ.) 46 2005-09-05 TA1383AFG 47 2005-09-05 |
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